1 /* ieee-utils/fp-darwin86.c
3 * Copyright (C) 2006 Erik Schnetter
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 3 of the License, or (at
8 * your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 #include <gsl/gsl_ieee_utils.h>
22 #include <gsl/gsl_errno.h>
24 /* Here is the dirty part. Set up your 387 through the control word
27 * 15-13 12 11-10 9-8 7-6 5 4 3 2 1 0
28 * | reserved | IC | RC | PC | reserved | PM | UM | OM | ZM | DM | IM
30 * IM: Invalid operation mask
31 * DM: Denormalized operand mask
32 * ZM: Zero-divide mask
35 * PM: Precision (inexact result) mask
37 * Mask bit is 1 means no interrupt.
39 * PC: Precision control
40 * 11 - round to extended precision
41 * 10 - round to double precision
42 * 00 - round to single precision
44 * RC: Rounding control
45 * 00 - rounding to nearest
46 * 01 - rounding down (toward - infinity)
47 * 10 - rounding up (toward + infinity)
48 * 11 - rounding toward zero
50 * IC: Infinity control
51 * That is for 8087 and 80287 only.
53 * The hardware default is 0x037f which we use.
56 /* masking of interrupts */
57 #define _FPU_MASK_IM 0x01
58 #define _FPU_MASK_DM 0x02
59 #define _FPU_MASK_ZM 0x04
60 #define _FPU_MASK_OM 0x08
61 #define _FPU_MASK_UM 0x10
62 #define _FPU_MASK_PM 0x20
64 /* precision control */
65 #define _FPU_EXTENDED 0x300 /* libm requires double extended precision. */
66 #define _FPU_DOUBLE 0x200
67 #define _FPU_SINGLE 0x0
69 /* rounding control */
70 #define _FPU_RC_NEAREST 0x0 /* RECOMMENDED */
71 #define _FPU_RC_DOWN 0x400
72 #define _FPU_RC_UP 0x800
73 #define _FPU_RC_ZERO 0xC00
75 #define _FPU_RESERVED 0xF0C0 /* Reserved bits in cw */
78 /* The fdlibm code requires strict IEEE double precision arithmetic,
79 and no interrupts for exceptions, rounding to nearest. */
81 #define _FPU_DEFAULT 0x037f
83 /* IEEE: same as above. */
84 #define _FPU_IEEE 0x037f
86 /* Type of the control word. */
87 typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__HI__)));
89 /* Macros for accessing the hardware control word.
91 Note that the use of these macros is no sufficient anymore with
92 recent hardware. Some floating point operations are executed in
93 the SSE/SSE2 engines which have their own control and status register. */
94 #define _FPU_GETCW(cw) __asm__ __volatile__ ("fnstcw %0" : "=m" (*&cw))
95 #define _FPU_SETCW(cw) __asm__ __volatile__ ("fldcw %0" : : "m" (*&cw))
97 /* Default control word set at startup. */
98 extern fpu_control_t __fpu_control;
102 #define _FPU_GETMXCSR(cw_sse) asm volatile ("stmxcsr %0" : "=m" (cw_sse))
103 #define _FPU_SETMXCSR(cw_sse) asm volatile ("ldmxcsr %0" : : "m" (cw_sse))
108 gsl_ieee_set_mode (int precision, int rounding, int exception_mask)
110 fpu_control_t mode, mode_sse;
113 mode &= _FPU_RESERVED ;
117 case GSL_IEEE_SINGLE_PRECISION:
118 mode |= _FPU_SINGLE ;
120 case GSL_IEEE_DOUBLE_PRECISION:
121 mode |= _FPU_DOUBLE ;
123 case GSL_IEEE_EXTENDED_PRECISION:
124 mode |= _FPU_EXTENDED ;
127 mode |= _FPU_EXTENDED ;
132 case GSL_IEEE_ROUND_TO_NEAREST:
133 mode |= _FPU_RC_NEAREST ;
135 case GSL_IEEE_ROUND_DOWN:
136 mode |= _FPU_RC_DOWN ;
138 case GSL_IEEE_ROUND_UP:
141 case GSL_IEEE_ROUND_TO_ZERO:
142 mode |= _FPU_RC_ZERO ;
145 mode |= _FPU_RC_NEAREST ;
148 if (exception_mask & GSL_IEEE_MASK_INVALID)
149 mode |= _FPU_MASK_IM ;
151 if (exception_mask & GSL_IEEE_MASK_DENORMALIZED)
152 mode |= _FPU_MASK_DM ;
154 if (exception_mask & GSL_IEEE_MASK_DIVISION_BY_ZERO)
155 mode |= _FPU_MASK_ZM ;
157 if (exception_mask & GSL_IEEE_MASK_OVERFLOW)
158 mode |= _FPU_MASK_OM ;
160 if (exception_mask & GSL_IEEE_MASK_UNDERFLOW)
161 mode |= _FPU_MASK_UM ;
163 if (exception_mask & GSL_IEEE_TRAP_INEXACT)
165 mode &= ~ _FPU_MASK_PM ;
169 mode |= _FPU_MASK_PM ;
174 _FPU_GETMXCSR (mode_sse) ;
175 mode_sse &= 0xFFFF0000 ;
177 if (exception_mask & GSL_IEEE_MASK_INVALID)
178 mode_sse |= _FPU_MASK_IM << 7 ;
180 if (exception_mask & GSL_IEEE_MASK_DENORMALIZED)
181 mode_sse |= _FPU_MASK_DM << 7 ;
183 if (exception_mask & GSL_IEEE_MASK_DIVISION_BY_ZERO)
184 mode_sse |= _FPU_MASK_ZM << 7 ;
186 if (exception_mask & GSL_IEEE_MASK_OVERFLOW)
187 mode_sse |= _FPU_MASK_OM << 7 ;
189 if (exception_mask & GSL_IEEE_MASK_UNDERFLOW)
190 mode_sse |= _FPU_MASK_UM << 7 ;
192 if (exception_mask & GSL_IEEE_TRAP_INEXACT)
194 mode_sse &= ~ _FPU_MASK_PM << 7 ;
198 mode_sse |= _FPU_MASK_PM << 7 ;
201 _FPU_SETMXCSR (mode_sse) ;